Typical memory circuits, such as static random access memory (SRAM) circuits, include a number of bitcells that can be written to and read from. Typically, the bitcells are arranged in an array, and individual bitcells can be addressed (for reading or writing) by selecting a corresponding column and row at which the bitcell is located in the array. Conventional bitcell designs typically include integrated row selection ports, but column selection is typically performed using circuitry external to the bitcell. For example, a NOR gate, or other suitable logic, can be added for column selection. Such approaches can have certain limitations, such as increasing area and power consumption of the memory circuit.